`timescale 1ns/1ns
module ds18b20_tb();
    reg             clk     ;
    reg             rst_n   ;
    reg             dq_in   ;
    wire            dq_out  ;
    wire            dq_en   ;
    ds18b20_driver          inst_ds18b20_driver(
        .clk                (clk     ),
        .rst_n              (rst_n   ),
        .dq_in              (dq_in   ),
        .dq_out             (dq_out  ),
        .dq_en              (dq_en   )
    );
    always #10 clk = ~clk;
    initial begin
        clk = 1'b0;
        rst_n = 1'b0;
        dq_in = 1'b0;
        #60;
        rst_n = 1'b1;
        #225000;
        $stop;
    end


endmodule
